YM2610
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http://www.ylw.mmtr.or.jp/~hosino/ma-net/sndgen/japanese/ym2610.htm
Pin Arrangement[edit]
_________ _________
_| \__/ |_
-> GND |_|1 64|_| øS -->
_| |_
<--> D0 |_|2 63|_| øM <--
_| |_
<--> D1 |_|3 62|_| VCC <--
_| |_
<--> D2 |_|4 61|_| A1 <--
_| |_
<--> D3 |_|5 60|_| A0 <--
_| |_
<--> D4 |_|6 59 _| /RD <--
_| |_
<--> D5 |_|7 58|_| /WR <--
_| |_
<--> D6 |_|8 57|_| /CS <--
_| |_
<--> D7 |_|9 56|_| /IRQ -->
_| |_
<--> RAD7 |_|10 55|_| PAD7 <-->
_| |_
<--> RAD6 |_|11 YAMAHA 54|_| PAD6 <-->
_| |_
<--> RAD5 |_|12 53|_| PAD5 <-->
_| YM2610 |_
<--> RAD4 |_|13 52|_| PAD4 <-->
_| |_
<--> RAD3 |_|14 51|_| PAD3 <-->
_| |_
<--> RAD2 |_|15 50|_| PAD2 <-->
_| |_
<--> RAD1 |_|16 49|_| PAD1 <-->
_| |_
<--> RAD0 |_|17 48|_| PAD0 <-->
_| |_
GND |_|18 47|_| PMPX -->
_| |_
VCC |_|19 46|_| /POE -->
_| |_
<-- RPMX |_|20 45|_| NC
_| |_
<-- /ROE |_|21 44|_| PA11 -->
_| |_
<-- RA9 |_|22 43|_| PA10 -->
_| |_
<-- RA8 |_|23 42|_| PA9 -->
_| |_
NC |_|24 41|_| PA8 -->
_| |_
NC |_|25 40|_| /TEST <--
_| |_
--> AGND |_|26 39|_| NC
_| |_
ANALOG OUT |_|27 38|_| RA23 -->
_| |_
--> AVCC |_|28 37|_| RA22 -->
_| |_
<-- SH2 |_|29 36|_| RA21 -->
_| |_
<-- SH1 |_|30 35|_| RA20 -->
_| |_
<-- OPO |_|31 34|_| NC
_| |_
GND |_|32 33|_| /1C
|______________________|
Terminal function
- øM Master clock (standard 8MHz) of OPNA is input.
- øS,SH1,SH2 It is clock (øS) for DAC and signal (SH1, SH2) of the cycle.
- OPO It is a serial data of FM, ADPCM, and rhythm each sound source part output.
- DO-D7 It is passing of interactive data of 8bit. CPU and data are exchanged.
- /CS, /RD, /WR, A1, A0 Data passing (D0-D7) is controlled.
- /IRQ The interrupt signal is output. It is an open drain output.
- ANALOG OUT It is an analog output terminal in the SSG sound source part. It is source for an output.
- RAD0-RAD7 Each signal of address (A0-A7), data input (D0-D7) of ADPCM-A
- RA8-RA9 Each signal of address (A8-A9) of ADPCM-A
- RA20-RA23 Each signal of address (A10-A14) of ADPCM-A
- /ROE ADPCM-A /OE
- RMPX Address control for data access of ADPCM-A
- PAD0-PAD7 Each signal of address (A0-A7), data input (D0-D7) of ADPCM-B
- PA8-PA11 Each signal of address (A8-A11) ) of ADPCM-B
- /POE ADPCM-B /OE
- PMPX Address control for data access of ADPCM-B
- /TEST It is a terminal for the test of LSI.
- GND,AGND It is a ground terminal.
- Vcc, AVcc It is a power supply terminal of +5V.
