Z80

From pcbotaku
Revision as of 00:15, 12 March 2011 by Invzim (talk | contribs) (Created page with "==Pin arrangement== _________ _________ _| \__/ |_ <-- A11 |_|1 40|_| A10 -...")
(diff) ← Older revision | Latest revision (diff) | Newer revision → (diff)
Jump to navigationJump to search

Pin arrangement

                   _________    _________
                 _|         \__/         |_                  
       <--  A11 |_|1                   40|_| A10  -->       
                 _|                      |_                  
       <--  A12 |_|2                   39|_| A9   -->        
                 _|                      |_                  
       <--  A13 |_|3       Z80 CPU     38|_| A8   -->        
                 _|                      |_                  
       <--  A14 |_|4                   37|_| A7   -->        
                 _|                      |_                  
       <--  A15 |_|5                   36|_| A6   -->
                 _|                      |_                  
        --> CLK |_|6                   35|_| A5   -->
                 _|                      |_
       <-->  D4 |_|7                   34|_| A4   -->
                 _|                      |_                  
       <-->  D3 |_|8                   33|_| A3   -->            
                 _|                      |_                  
       <-->  D5 |_|9                   32|_| A2   -->            
                 _|                      |_                  
       <-->  D6 |_|10                  31|_| A1   -->            
                 _|                      |_                  
            VCC |_|11                  30|_| A0   -->           
                 _|                      |_                  
       <-->  D2 |_|12                  29|_| GND           
                 _|                      |_                  
       <-->  D7 |_|13                  28|_| /RFSH -->          
                 _|                      |_                  
       <-->  D0 |_|14                  27|_| /M1  -->           
                 _|                      |_                  
       <-->  D1 |_|15                  26|_| /RESET <--      
                 _|                      |_                  
       --> /INT |_|16                  25|_| /BUSRQ <--      
                 _|                      |_                  
       --> /NMI |_|17                  24|_| /WAIT <--      
                 _|                      |_                  
      <-- /HALT |_|18                  23|_| /BUSAK -->     
                 _|                      |_                  
      <-- /MREQ |_|19                  22|_| /WR  -->       
                 _|                      |_                  
      <-- /IORQ |_|20                  21|_| /RD  -->       
                  |______________________|
  • C/D CONTROL=1
  • DATA=0
  • B/A PORT B=1
  • PORT A=0