TC531001: Difference between revisions

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MASK ROM, 1MBit (128K x 8), 131 072 bytes.
==TC531001CP/CF-12/15==
==TC531001CP/CF-12/15==


                   _________    _________
                   _________    _________
Line 37: Line 40:


==Pin arrangement==
==Pin arrangement==
#A0-A16 Address Inputs
*A0-A16 Address Inputs
#D0-D7 Data Outputs
*D0-D7 Data Outputs
#/OE Data Enable Input
*/OE Data Enable Input
#/CE Chip Enable Input
*/CE Chip Enable Input
#VDD Power supply
*VDD Power supply
#GND Ground
*GND Ground
#N.C. No Connection
*N.C. No Connection
 
==Datasheet==
[[File:TC531001.pdf]]


[[category:IC]]
[[category:IC]]

Latest revision as of 21:42, 27 March 2011

MASK ROM, 1MBit (128K x 8), 131 072 bytes.

TC531001CP/CF-12/15[edit]

                  _________    _________
                _|         \__/         |_
           N.C |_|1                   32|_| VDD
                _|                      |_
           A16 |_|2                   31|_| N.C
                _|                      |_
           A15 |_|3                   30|_| N.C
                _|                      |_
           A12 |_|4                   29|_| A14
                _| TC531001CP/CF-12/15  |_
            A7 |_|5                   28|_| A13
                _|                      |_
            A6 |_|6                   27|_| A8
                _|                      |_
            A5 |_|7                   26|_| A9
                _|                      |_
            A4 |_|8                   25|_| A11
                _|                      |_
            A3 |_|9                   24|_| /OE
                _|                      |_
            A2 |_|10                  23|_| A10
                _|                      |_
            A1 |_|11                  22|_| /CE
                _|                      |_
            A0 |_|12                  21|_| D7
                _|                      |_
            D0 |_|13                  20|_| D6
                _|                      |_
            D1 |_|14                  19|_| D5
                _|                      |_
            D2 |_|15                  18|_| D4
                _|                      |_
          GND  |_|16                  17|_| D3
                 |______________________|

Pin arrangement[edit]

  • A0-A16 Address Inputs
  • D0-D7 Data Outputs
  • /OE Data Enable Input
  • /CE Chip Enable Input
  • VDD Power supply
  • GND Ground
  • N.C. No Connection

Datasheet[edit]

File:TC531001.pdf