Z80 - Revision history

Invzim at 09:33, 29 March 2011

2011-03-29T09:33:35Z

← Older revision		Revision as of 09:33, 29 March 2011
Line 78:		Line 78:
	===CLK===		===CLK===
	Clock (input). Single-phase MOS-level clock.		Clock (input). Single-phase MOS-level clock.
			==References==
			[[File:Z80cpu um.pdf]] - Z80 User Manual

Invzim at 09:25, 29 March 2011

2011-03-29T09:25:26Z

← Older revision		Revision as of 09:25, 29 March 2011
Line 48:		Line 48:
	===A15–A0 Address Bus===		===A15–A0 Address Bus===
	(output, active High, tristate). A15-A0 form a 16-bit address bus. The Address Bus provides the address for memory data bus exchanges (up to 64 Kbytes) and for I/O device exchanges.		(output, active High, tristate). A15-A0 form a 16-bit address bus. The Address Bus provides the address for memory data bus exchanges (up to 64 Kbytes) and for I/O device exchanges.

	===D7–D0===		===D7–D0===
	Data Bus (input/output, active High, tristate). D7–D0 constitute an 8-bit bidirectional data bus, used for data exchanges with memory and I/O.		Data Bus (input/output, active High, tristate). D7–D0 constitute an 8-bit bidirectional data bus, used for data exchanges with memory and I/O.


	===/BUSACK===		===/BUSACK===
	Bus Acknowledge (output, active Low). Bus Acknowledge indicates to the requesting device that the CPU address bus, data bus, and control signals MREQ, IORQ RD, and WR have entered their high-impedance states. The external circuitry can now control these lines.		Bus Acknowledge (output, active Low). Bus Acknowledge indicates to the requesting device that the CPU address bus, data bus, and control signals MREQ, IORQ RD, and WR have entered their high-impedance states. The external circuitry can now control these lines.

	===/BUSREQ===		===/BUSREQ===
	Bus Request (input, active Low). Bus Request has a higher priority than NMI and is always recognized at the end of the current machine cycle. BUSREQ forces the CPU address bus, data bus, and control signals MREQ IORQ, RD, and WR to go to a high-impedance state so that other devices can control these lines. BUSREQ is normally wired-OR and requires an external pull-up for these applications. Extended BUSREQ periods due to extensive DMA operations can prevent the CPU from properly refreshing dynamic RAMS.		Bus Request (input, active Low). Bus Request has a higher priority than NMI and is always recognized at the end of the current machine cycle. BUSREQ forces the CPU address bus, data bus, and control signals MREQ IORQ, RD, and WR to go to a high-impedance state so that other devices can control these lines. BUSREQ is normally wired-OR and requires an external pull-up for these applications. Extended BUSREQ periods due to extensive DMA operations can prevent the CPU from properly refreshing dynamic RAMS.

	===/HALT===		===/HALT===
	HALT State (output, active Low). HALT indicates that the CPU has executed a HALT instruction and is waiting for either a non-maskable or a maskable interrupt (with the mask enabled) before operation can resume. During HALT, the CPU executes NOPs to maintain memory refresh.		HALT State (output, active Low). HALT indicates that the CPU has executed a HALT instruction and is waiting for either a non-maskable or a maskable interrupt (with the mask enabled) before operation can resume. During HALT, the CPU executes NOPs to maintain memory refresh.

	===/INT===		===/INT===
	Interrupt Request (input, active Low). Interrupt Request is generated by I/O devices. The CPU honors a request at the end of the current instruction if the internal software-controlled interrupt enable flip-flop (IFF) is enabled. INT is normally wired-OR and requires an external pull-up for these applications.		Interrupt Request (input, active Low). Interrupt Request is generated by I/O devices. The CPU honors a request at the end of the current instruction if the internal software-controlled interrupt enable flip-flop (IFF) is enabled. INT is normally wired-OR and requires an external pull-up for these applications.

	===/IORQ===		===/IORQ===
	Input/Output Request (output, active Low, tristate). IORQ indicates that the lower half of the address bus holds a valid I/O address for an I/O read or write operation. IORQ is also generated concurrently with M1 during an interrupt acknowledge cycle to indicate that an interrupt response vector can be placed on the data bus.		Input/Output Request (output, active Low, tristate). IORQ indicates that the lower half of the address bus holds a valid I/O address for an I/O read or write operation. IORQ is also generated concurrently with M1 during an interrupt acknowledge cycle to indicate that an interrupt response vector can be placed on the data bus.

	===/M1===		===/M1===
	Machine Cycle One (output, active Low). M1, together with MREQ, indicates that the current machine cycle is the opcode fetch cycle of an instruction execution. M1 together with IORQ, indicates an interrupt acknowledge cycle.		Machine Cycle One (output, active Low). M1, together with MREQ, indicates that the current machine cycle is the opcode fetch cycle of an instruction execution. M1 together with IORQ, indicates an interrupt acknowledge cycle.

	===/MREQ===		===/MREQ===
	Memory Request (output, active Low, tristate). MREQ indicates that the address bus holds a valid address for a memory read of memory write operation.		Memory Request (output, active Low, tristate). MREQ indicates that the address bus holds a valid address for a memory read of memory write operation.

	===/NMI===		===/NMI===
	Non-Maskable Interrupt (input, negative edge-triggered). NMI has a higher priority than INT. NMI is always recognized at the end of the current instruction, independent of the status of the interrupt enable flip-flop, and automatically forces the CPU to restart at location 0066H.		Non-Maskable Interrupt (input, negative edge-triggered). NMI has a higher priority than INT. NMI is always recognized at the end of the current instruction, independent of the status of the interrupt enable flip-flop, and automatically forces the CPU to restart at location 0066H.

	===/RD===		===/RD===
	Read (output, active Low, tristate). RD indicates that the CPU wants to read data from memory or an I/O device. The addressed I/O device or memory should use this signal to gate data onto the CPU data bus.		Read (output, active Low, tristate). RD indicates that the CPU wants to read data from memory or an I/O device. The addressed I/O device or memory should use this signal to gate data onto the CPU data bus.

	===/RESET===		===/RESET===
	Reset (input, active Low). RESET initializes the CPU as follows: it resets the interrupt enable flip-flop, clears the PC and registers I and R, and sets the interrupt status to Mode 0. During reset time, the address and data bus go to a high-impedance state, and all control output signals go to the inactive state. Notice that RESET must be active for a minimum of three full clock cycles before the reset operation is complete.		Reset (input, active Low). RESET initializes the CPU as follows: it resets the interrupt enable flip-flop, clears the PC and registers I and R, and sets the interrupt status to Mode 0. During reset time, the address and data bus go to a high-impedance state, and all control output signals go to the inactive state. Notice that RESET must be active for a minimum of three full clock cycles before the reset operation is complete.

	===/RFSH===		===/RFSH===
	Refresh (output, active Low). RFSH, together with MREQ indicates that the lower seven bits of the system’s address bus can be used as a refresh address to the system’s dynamic memories.		Refresh (output, active Low). RFSH, together with MREQ indicates that the lower seven bits of the system’s address bus can be used as a refresh address to the system’s dynamic memories.

	===/WAIT===		===/WAIT===
	WAIT (input, active Low). WAIT communicates to the CPU that the addressed memory or I/O devices are not ready for a data transfer. The CPU continues to enter a WAIT state as long as this signal is active. Extended WAIT periods can prevent the CPU from properly refreshing dynamic memory.		WAIT (input, active Low). WAIT communicates to the CPU that the addressed memory or I/O devices are not ready for a data transfer. The CPU continues to enter a WAIT state as long as this signal is active. Extended WAIT periods can prevent the CPU from properly refreshing dynamic memory.

	===/WR===		===/WR===
	Write (output, active Low, tristate). WR indicates that the CPU data bus holds valid data to be stored at the addressed memory or I/O location.		Write (output, active Low, tristate). WR indicates that the CPU data bus holds valid data to be stored at the addressed memory or I/O location.

	===CLK===		===CLK===
	Clock (input). Single-phase MOS-level clock.		Clock (input). Single-phase MOS-level clock.

Invzim at 09:24, 29 March 2011

2011-03-29T09:24:40Z

@@ Line 34: / Line 34: @@
          <-->  D1 |_|15                  26|_| /RESET <--
                    _|                      |_
-         --> /INT |_|16                  25|_| /BUSRQ <--
+         --> /INT |_|16                  25|_| /BUSREQ <--
                    _|                      |_
          --> /NMI |_|17                  24|_| /WAIT <--
                    _|                      |_
-        <-- /HALT |_|18                  23|_| /BUSAK -->
+        <-- /HALT |_|18                  23|_| /BUSACK -->
                    _|                      |_
         <-- /MREQ |_|19                  22|_| /WR  -->
@@ Line 45: / Line 45: @@
                     |______________________|
-*C/D  CONTROL=1
+==Pin Functions==
-*DATA=0
+===A15–A0 Address Bus===
-*B/A  PORT B=1
+(output, active High, tristate). A15-A0 form a 16-bit address bus. The Address Bus provides the address for memory data bus exchanges (up to 64 Kbytes) and for I/O device exchanges.
-*PORT A=0

Invzim at 00:16, 12 March 2011

2011-03-12T00:16:01Z

← Older revision		Revision as of 00:16, 12 March 2011
Line 1:		Line 1:
			[[CATEGORY:IC]]
			[[CATEGORY:CPU]]
	==Pin arrangement==		==Pin arrangement==
	_________ _________		_________ _________

Invzim: Created page with "==Pin arrangement== _ _ _| \__/ |_ <-- A11 |_|1 40|_| A10 -..."

2011-03-12T00:15:21Z

Created page with "==Pin arrangement== _________ _________ _| \__/ |_ <-- A11 |_|1 40|_| A10 -..."

New page

==Pin arrangement==
_________ _________
_| \__/ |_
<-- A11 |_|1 40|_| A10 -->
_| |_
<-- A12 |_|2 39|_| A9 -->
_| |_
<-- A13 |_|3 Z80 CPU 38|_| A8 -->
_| |_
<-- A14 |_|4 37|_| A7 -->
_| |_
<-- A15 |_|5 36|_| A6 -->
_| |_
--> CLK |_|6 35|_| A5 -->
_| |_
<--> D4 |_|7 34|_| A4 -->
_| |_
<--> D3 |_|8 33|_| A3 -->
_| |_
<--> D5 |_|9 32|_| A2 -->
_| |_
<--> D6 |_|10 31|_| A1 -->
_| |_
VCC |_|11 30|_| A0 -->
_| |_
<--> D2 |_|12 29|_| GND
_| |_
<--> D7 |_|13 28|_| /RFSH -->
_| |_
<--> D0 |_|14 27|_| /M1 -->
_| |_
<--> D1 |_|15 26|_| /RESET <--
_| |_
--> /INT |_|16 25|_| /BUSRQ <--
_| |_
--> /NMI |_|17 24|_| /WAIT <--
_| |_
<-- /HALT |_|18 23|_| /BUSAK -->
_| |_
<-- /MREQ |_|19 22|_| /WR -->
_| |_
<-- /IORQ |_|20 21|_| /RD -->
|______________________|

*C/D CONTROL=1
*DATA=0
*B/A PORT B=1
*PORT A=0

Z80 - Revision history

Invzim at 09:33, 29 March 2011

Invzim at 09:25, 29 March 2011

Invzim at 09:24, 29 March 2011

Invzim at 00:16, 12 March 2011

Invzim: Created page with "==Pin arrangement== _________ _________ _| \__/ |_ <-- A11 |_|1 40|_| A10 -..."

Invzim: Created page with "==Pin arrangement== _ _ _| \__/ |_ <-- A11 |_|1 40|_| A10 -..."