CPS2 PAL3 - Revision history

Invzim: /* B-board qsound routing error */

2012-09-28T21:48:59Z

B-board qsound routing error

← Older revision		Revision as of 21:48, 28 September 2012
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	===B-board qsound routing error===		===B-board qsound routing error===
	These earlier boards have what is suspected to be a PCB layout error, routing the qsound address line found on CN3 pin C14 to pin 9 of PAL3, instead of a higher address line found on CN3 pin 13. This results in garbled sounds because the address lines are not decoded properly when using the G pal (2x4mb eproms).

	*93646B-3		*93646B-3
	*93646B-4		*93646B-4

			These earlier boards have what is suspected to be a PCB layout error affecting games that use the G PAL. Instead of routing the high address line of the qsound samples to to pin9 of PAL3, it instead routes a low address line. This results in garbled sounds.

			To fix this, lift pin9 of PAL3 out of socket and solder a jumper wire from it to pin C13 on connector CN3.

	===On rom board 93646B-4===		===On rom board 93646B-4===

2012-09-28T13:38:56Z

PAL/GAL images

← Older revision		Revision as of 13:38, 28 September 2012
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	==PAL/GAL images==		==PAL/GAL images==
	http://www.jammarcade.net/pal-dumps/		http://www.jammarcade.net/pal-dumps/

	~~''As of 21 Sept 2012 - the G Pal from jamma arcade is not confirmed working, F version works great''~~

	==PAL3==		==PAL3==

2012-09-27T23:27:51Z

PAL3

← Older revision		Revision as of 23:27, 27 September 2012
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	==PAL3==		==PAL3==
	Deals with addressing the ROMS, 4(5) different versions. Original part is PALCE16V8H-15, 15 is the speed rating, 15ns. Pin compatible GAL is GAL16V8B-15, GAL16V8B-10 is also confirmed working.		Deals with addressing the ROMS, 4(5) different versions. Original part is PALCE16V8H-15, 15 is the speed rating, 15ns. Pin compatible GAL is GAL16V8B-15, GAL16V8B-10 is also confirmed working.

			===B-board qsound routing error===
			These earlier boards have what is suspected to be a PCB layout error, routing the qsound address line found on CN3 pin C14 to pin 9 of PAL3, instead of a higher address line found on CN3 pin 13. This results in garbled sounds because the address lines are not decoded properly when using the G pal (2x4mb eproms).

			*93646B-3
			*93646B-4


	===On rom board 93646B-4===		===On rom board 93646B-4===

2012-09-25T23:11:23Z

Version E

← Older revision		Revision as of 23:11, 25 September 2012
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	i1=1 i2=2 i4=4 i5=5 i7=7 GND=10 /nc11=11 o12=12 o13=13 o14=14 o15=15 o16=16 o17=17 o18=18 o19=19 VCC=20		i1=1 i2=2 i4=4 i5=5 i7=7 GND=10 /nc11=11 o12=12 o13=13 o14=14 o15=15 o16=16 o17=17 o18=18 o19=19 VCC=20

	/o19 = i2 * /i1		/o19 = i2 * /i1 output pin 19 is the enable line on eprom 14&16
	/o18 = /i2 * /i1		/o18 = /i2 * /i1 output pin 18 is the enable line on eprom 13&15
	/o17 = /i4 * i5		/o17 = /i4 * i5 output pin 17 is the enable line on eprom 18&20
	/o16 = /i4 * /i5		/o16 = /i4 * /i5 output pin 16 is the enable line on eprom 17&19
	/o15 = /i7		/o15 = /i7 output pin 15 is the enable line on eprom 11
	/o14 = i7		/o14 = i7 output pin 14 is the enable line on eprom 12
	/o13 = gnd		/o13 = gnd
	/o12 = vcc		/o12 = vcc

2012-09-25T23:09:16Z

Version E

2012-09-25T23:05:37Z

Version D

← Older revision		Revision as of 23:05, 25 September 2012
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	i1=1 i2=2 i3=3 i4=4 i5=5 i6=6 i7=7 GND=10 /nc11=11 o12=12 o13=13 o14=14 o15=15 o16=16 o17=17 o18=18 o19=19 VCC=20		i1=1 i2=2 i3=3 i4=4 i5=5 i6=6 i7=7 GND=10 /nc11=11 o12=12 o13=13 o14=14 o15=15 o16=16 o17=17 o18=18 o19=19 VCC=20

	/o19 = /i2 * i1 * /i3 output pin 19 is the enable line on eprom 14&16		/o19 = /i2 * i1 * /i3 output pin 19 is the enable line on eprom 14&16
	o18 = i1 output pin 18 is the enable line on eprom 13&15		o18 = i1 output pin 18 is the enable line on eprom 13&15

2012-09-25T23:04:37Z

Version D

@@ Line 23: / Line 23: @@
 ==Version D==
 Unknown
 ==Version E==

2012-09-25T20:39:22Z

Version F

← Older revision		Revision as of 20:39, 25 September 2012
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	Up to 32mbit GFX, 2x2mb qsound sample eproms		Up to 32mbit GFX, 2x2mb qsound sample eproms

			i1=1 i4=4 i7=7 GND=10 /nc11=11 o12=12 o13=13 o14=14 o15=15 o16=16 o17=17 o18=18 o19=19 VCC=20

			/o19 = i1 output pin 19 is the enable line on eprom 14&16
			o18 = i1 output pin 18 is the enable line on eprom 13&15
			/o17 = i4 output pin 17 is the enable line on eprom 18&20
			o16 = i4 output pin 16 is the enable line on eprom 17&19
			o15 = i7 output pin 15 is the enable line on eprom 11
			/o14 = i7 output pin 14 is the enable line on eprom 12
			/o13 = gnd
			/o12 = vcc

	==Version G==		==Version G==

2012-09-25T20:38:01Z

Version G

2012-09-25T20:19:25Z

Version G

← Older revision		Revision as of 20:19, 25 September 2012
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	The equations, or logic, of this chip is:		The equations, or logic, of this chip is:
	i1=1 i4=4 i9=9 GND=10 /nc11=11 o12=12 o13=13 o14=14 o15=15 o16=16 o17=17 o18=18 o19=19 VCC=20		i1=1 i4=4 i9=9 GND=10 /nc11=11 o12=12 o13=13 o14=14 o15=15 o16=16 o17=17 o18=18 o19=19 VCC=20

	o19 = /i1 output pin 19 is the enable line on eprom 14&16		o19 = /i1 output pin 19 is the enable line on eprom 14&16
	o18 = i1 output pin 18 is the enable line on eprom 13&15		o18 = i1 output pin 18 is the enable line on eprom 13&15